This invention relates to a corrective device for an inverter output voltage error wherein the error of an inverter output voltage attributed to a short-circuit preventive period is detected and is corrected so as to become smaller.
FIG. 1 is a block connection diagram in which a prior-art inverter control circuit shown in, for example, Collection of Papers of `Intelec 83` (Oct. 18-21, Tokyo), pp. 205-212, Sekino et al.; Inverter Output Voltage Waveform Closed Loop Control Technique, is redrafted. Referring to the figure, numeral 1 designates an inverter main circuit. Numerals 2 and 3 designate a reactor and a capacitor, respectively, which constitute an A.C. filter. Numeral 4 indicates a D.C. power source, numeral 5 a load, numeral 7 a drive circuit for the inverter main circuit 1, numeral 8 an A.C. reference voltage generator circuit for generating a reference voltage having the shape of a sinusoidal wave, and numeral 9 an amplifier. Shown at numeral 10 is a PWM (pulse-width modulation) circuit, which is configured of a comparator circuit 10a and a carrier wave generator circuit 10b.
In addition, FIG. 2 shows a diagram of the conventional arrangement of the inverter main circuit 1. This circuit has transistors 17, 18, 19 and 20, and feedback diodes 17a, 18a, 19a and 20a. The load 5, and the reactor 2 and capacitor 3 of the A.C. filter are incorporated as illustrated in the figure. Numeral 14 indicates a D.C. supply voltage V.sub.D.
Next, the operation of the prior-art circuit will be described.
First, a sinusoidal output voltage 15 corresponding to the control output of the PWM circuit 10 is produced across the terminals of the capacitor 3. Meanwhile, the amplifier 9 and the PWM circuit 10 control the switching of the inverter main circuit 1 so that the output voltage may agree with the sinusoidal wave reference of the A.C. reference voltage generator circuit 8.
Besides, the PWM circuit 10 is constructed of the comparator circuit 10a and the circuit 10b for generating a triangular carrier wave, and it determines the switching point of time of PWM on the basis of a substantially sinusoidal signal from the amplifier 9 as has been obtained by amplifying the deviation of the output voltage. In actuality, the amplifier 9 has only a finite gain from the standpoint of stability. Therefore, the inverter operates in such a manner that the output voltage thereof follows up the reference voltage of the A.C. reference voltage generator circuit 8 with some deviation from the reference voltage.
Waveforms in FIG. 3 represent the ideal values (in a solid line) and actual values (in a broken line) of a potential which is applied to a point a at one end of the load 5, under the assumption that the middle point of the D.C. power source V.sub.D in FIG. 2 is at the ground potential. Further, a sinusoidal wave represents a load current I.
Referring also to FIG. 3, during a period of time 21, the transistors 17 and 20 are "on", and hence, a voltage of +V.sub.D /2 is applied to the point a of the load 5. On this occasion, a voltage of -V.sub.D /2 is applied to a point b at the other end of the load 5, so that a voltage of +V.sub.D is eventually applied across the load 5. Here, the potentials of the points a and b are actually influenced by the reactor 2 and the capacitor 3. During a period of time 23, the transistors 19 and 18 are "on", and hence, the voltage of -V.sub.D /2 is applied to the point a of the load 5. On this occasion, the voltage of +V.sub.D /2 is applied to the point b, so that a voltage of -V.sub.D is eventually applied across the load 5.
The solid-line rectangular wave in FIG. 3 is a waveform at the point a in the case where the above two statuses are alternately repeated under the condition of a null transition time.
In actuality, a short-circuit preventive period T.sub.d is set at the transition between the two statuses in order to avoid the overcurrent breakdown of the transistors attributed to the "on" and "off" delays of the individual transistors. (The overcurrent breakdown is elucidated as follows: By way of example, in the course of the transition from the status under which the transistors 17 and 20 are "on" with the transistors 18 and 19 being "off", to the status under which the transistors 17 and 20 are "off" with the transistors 18 and 19 being "on", the turn-off of the transistor 17 or 20 is assumed to be delayed with respect to the turn-on of the transistor 18 or 19. Then, the transistors 17 and 18 or the transistors 19 and 20 are simultaneously turned "on" during the period of the delay, and both the terminals of the D.C. power source 4 are short-circuited in the meantime. Consequently, the transistors 17 and 18, or 19 and 20 lead to the breakdown due to an overcurrent flowing therethrough.) The short-circuit preventive period T.sub.d is so selected that the turn-on of the transistor to change-over from the "off" state to the "on" state is retarded, thereby to prevent the occurrence of the moment at which the transistor 17 or 19 connected to the plus side of the D.C. power source 4 and the transistor 18 or 20 connected to the minus side thereof are both turned "on".
The rectangular wave indicated by the broken line in FIG. 3 is the actual voltage which is applied to the point a in the case of setting the short-circuit preventive period T.sub.d.
The transistors 17 and 20 change from the "on" states into the "off" states at the point of time of a transition 22, whereupon the transistors 18 and 19 turn "on" from the "off" states with the delay T.sub.d. During the short-circuit preventive period T.sub.d, all the transistors are "off", but the load current I continues to flow from the point a to the point b on the basis of the reactor 2 for the filter and the inductance of the load 5. As indicated by an arrow, the path of this load current I extends along the minus side of the D.C. power source 4 .fwdarw. the diode 18a .fwdarw. the load 5 .fwdarw. the diode 19a .fwdarw. the plus side of the D.C. power source 4. As a result, the potential of the point a becomes -V.sub.D /2, and that of the point b becomes +V.sub.D /2. At the point of time of the transition 22, accordingly, the same voltage waveform as the ideal value is established without the influence of the short-circuit preventive period T.sub.d.
The transistors 18 and 19 change from the "on" states into the "off" states in a period of time 24, whereupon the transistors 17 and 20 turn "on" from the "off" states with the delay of the short-circuit preventive period T.sub.d. Also during this short-circuit preventive period T.sub.d, all the transistors are "off", and the direction of the current is the same as in the foregoing, so that the potential of the point a becomes -V.sub.D /2 similarly to the above. The transistors 17 and 20 turn "on" after the short-circuit preventive period T.sub.d, so that the potential of the point a becomes +V.sub.D /2. As a result, the potential of the point a delays for the short-circuit preventive period T.sub.d relative to the ideal value. Insofar as the load current I is flowing in the same direction as in the foregoing, an error voltage ascribable to this delay has a minus value and develops every cycle of the rectangular wave. The average of such minus values corresponds to the first half of the waveform of a mean error voltage (V.sub.TD) 26.
Incidentally, in a case where the load current I is flowing in the direction opposite to the foregoing, such an error voltage arises in the period of time in which the transistors 17 and 20 change from the "on" states into the "off" states, followed by the turn-on of the transistors 18 and 19 with the delay of the short-circuit preventive period T.sub.d. Insofar as the load current I is flowing in the opposite direction, this error voltage has a plus value and develops every cycle of the rectangular wave. The average of such plus values corresponds to the latter half of the waveform of the mean error voltage V.sub.TD) 26.
Since the prior-art corrective device for the inverter output voltage error is constructed as described above, all the transistors across both the poles of individual arms are turned "off" for the predetermined short-circuit preventive period (T.sub.d) so as to cease the inverter output voltage for the purpose of preventing the arms from short-circuiting during the commutations of the transistors. As a result, the prior-art device has had such a problem that the output voltage involves the error which corresponds to the difference between the actual inverter voltage value indicated by the broken line and the ideal inverter voltage value indicated by the solid line.